Qwen3.6-35B-A3B MTPLX Optimized Speed FP16

FP16 compatibility sibling for Youssofal/Qwen3.6-35B-A3B-MTPLX-Optimized-Speed, packaged for MTPLX native Multi-Token-Prediction speculative decoding on older Apple Silicon.

This variant keeps the same release model family as Qwen3.6-35B-A3B Optimized Speed. Packed quantized tensors stay packed; BF16 floating tensors are converted to FP16 so M1 and M2 Macs can use the FP16-friendly path without changing the artifact's intended speed/quality tier.

Run It

brew install youssofal/mtplx/mtplx
mtplx start
mtplx run "hello" --model Youssofal/Qwen3.6-35B-A3B-MTPLX-Optimized-Speed-FP16

For an OpenAI-compatible local server:

mtplx serve --model Youssofal/Qwen3.6-35B-A3B-MTPLX-Optimized-Speed-FP16 --profile sustained --max --port 8000 --no-stats-footer

Device Routing

M1/M2 Apple Silicon: MTPLX may prefer this FP16 sibling.
M3/M4/M5 Apple Silicon: MTPLX keeps the normal optimized artifact by default.
Explicit --model always wins.

Recommended Runtime Defaults

Setting	Value
Backend	`qwen3-next-mtp`
Default depth	`D1`
Profile	`sustained`
Precision policy	preserve packed tensors; convert BF16 floats to FP16

Source Performance Baseline

These are the source artifact numbers used as the regression baseline. The FP16 variant should stay close, but it is primarily a device-compatibility release.

Mode	TPS	Verify time	Acceptance
AR baseline	94.46	-	-
D1 promoted default	138.38	69.30s	0.8858
D2 promoted default	135.66	49.23s	0.8701, 0.6409
D3 comparison	107.67	46.45s	0.8291, 0.5414, 0.2783

Model Build

Component	Format
Main body	4-bit MLX affine body with BF16 float leaves converted to FP16
MTP sidecar	same MTP policy as source; BF16 float leaves converted to FP16
Packed quantized tensors	preserved without requantization
Manifest	`MTPLX_FP16_CONVERSION_MANIFEST.json` records tensor-level conversions

This is not a full-precision checkpoint. It is built for fast local use on Apple Silicon through MTPLX.