Thaki-HW-27B v0.1 — Research Preview

Engineering blog: Our RTL Fine-Tune of a 27B Model Did Not Beat the Base (한국어: 블로그)

A hardware-design (Verilog RTL) fine-tune of Qwen/Qwen3.8-27B (revision 1d4bf0f2ff6012fd82039f2fa52739d0dd7c60c0), released by ThakiCloud. Architecture, tokenizer, vision encoder and chat template are unchanged from the base; a rank-8 LoRA on the language model was merged into bf16 weights.

Research Preview — an early research checkpoint, not a validated hardware-specialised model. Trained by ThakiCloud on Qwen3.8-27B with a self-built RTL dataset: licence-traced RTL seeds and self-distilled code kept only when formally equivalent (bounded) to the source. It met the pre-registered release criteria on VerilogEval, RTLLM and general coding, but no statistically significant improvement over the base Qwen3.8-27B was found, and a possible regression on RTLLM is not ruled out (Δ −4.27pp, 95% CI [−12.82, +4.27]; RTLLM compile rate −8.55pp). Improvements in complex FPGA/GPU/NPU design are not demonstrated. For production use, prefer the base model; use this checkpoint for research and experimentation.

Evaluation (same harness for base and this model)

Qwen3.8 thinking mode on, max 65,536 output tokens, vLLM 0.29 bf16, model-card sampling (T=1.0, top_p=0.95, top_k=20). Task-level paired bootstrap (B=10,000, seed 20261003), 95% CI. Pre-registered gates in docs/d59/prereg.md of the training repository.

Compile rate is a reference metric only (Δ compile VerilogEval +2.14pp, RTLLM -8.55pp; compile-up/functional-flat pattern fired: False). "correct" counts are task-level pass rates summed over tasks (k samples averaged per task). The RTLLM point estimate is negative (-4.27pp, about 1.7 tasks) but its CI includes zero; the coding benchmark is near ceiling for the base (0.98), so it can only detect drops. One VerilogEval task weighs 0.64pp, one RTLLM task 2.56pp, one coding item 0.15pp. Single training run; retraining noise is unmeasured.

Training data (what it actually is)

• 1000 spec→RTL rows. Seeds are Verilog modules from ESCAD/OpenRTLSet whose upstream repository licence is permissive per row (mit: 723, apache-2.0: 205, bsd-3-clause: 41, bsd-2-clause: 25, cc0-1.0: 6); descriptions come from theepicflyer/openrtlset-permissive-verified (LLM-written descriptions reverse-generated from the source RTL — not independent specifications; the module interface is pinned).
• The target code was generated by Qwen3.8-27B itself (non-thinking mode, 4–8 samples per seed) and kept only if Yosys proved it equivalent to the source RTL (sat -seq 50 -set-init-zero for sequential, SAT for combinational). This is bounded equivalence to a reference, not proof of functional correctness against a specification. At most one sample per seed. The source RTL itself was not used as a training target.
• Filters: row-level SPDX allow-list (rows whose code also appears under a non-permissive licence were dropped), generator repositories removed, Verilator lint + single top module, decontamination against VerilogEval, RTLLM, HWE-Bench, AcceleratorBench and an internal sealed benchmark (exact, normalized, near-duplicate and containment axes), deduplication.
• 317 general-coding replay rows (OpenCodeInstruct CC-BY-4.0, CommitPackFT permissive subset).
• Format: non-thinking chat turns (enable_thinking=false); no reasoning traces were trained. Thinking-mode behaviour is inherited from the base.

Recipe

LoRA r=8, alpha=16, all language-model linear layers incl. linear-attention projections (vision tower frozen), lr 5e-5 constant, 1 epoch, batch 1, max length 2,048, 1317 optimizer steps (lr×steps ≈ 0.066), fp32 merge into bf16 base weights. Merge was checked against the unmerged LoRA model (fp32 logit max |Δ| ≤ 1e-2; non-target tensors bit-identical).

Limitations

• Small pilot (1000 rows, one run). FIFO (5) and accelerator-datapath (10) examples are scarce: the base model rarely solved them, and the equivalence checker cannot model memories/latches, so those families are under-represented.
• Benchmarks are single-module spec-to-RTL and general Python coding; repository-level engineering is not evaluated here.
• Self-distillation sharpens what the base already solves; it does not add capabilities the base lacks.
• Post-release data audit: an independent differential-simulation audit of the 1,000 training examples observed output mismatches in 27 examples and could not decide 244 examples. Some mismatches may stem from differences in the simulation environment; the actual rate of functional errors in the training data has not been established. These examples were trained on; the model was not retrained.

Licence and attribution

Model weights: Apache-2.0 (as the base). Training code seeds remain under their upstream licences; attribution list:

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Thaki-HW-27B v0.1 — Research Preview (한국어)

기술 블로그: RTL로 학습한 27B는 원본을 이기지 못했습니다 (English: blog)

Qwen/Qwen3.8-27B(revision 1d4bf0f2ff6012fd82039f2fa52739d0dd7c60c0)를 하드웨어 설계(Verilog RTL)용으로 미세조정했다. 아키텍처·토크나이저·비전 인코더·채팅 템플릿은 원본과 같다. 언어 모델에 rank-8 LoRA 를 학습한 뒤 bf16 가중치에 병합했다.

Research Preview — 연구 및 실험을 위한 초기 체크포인트이며, 검증된 하드웨어 특화 모델이 아닙니다. ThakiCloud에서 Qwen3.8-27B를 기반으로 자체 구축한 RTL 데이터셋을 사용하여 학습한 하드웨어 설계 연구 모델입니다. 라이선스 계보를 확인한 RTL 코드와 형식적 동치 검증을 활용한 자가증류 데이터로 학습했습니다. VerilogEval, RTLLM 및 일반 코딩 평가에서 사전등록된 공개 기준을 충족했지만, 원본 Qwen3.8-27B 대비 통계적으로 유의한 성능 향상은 확인되지 않았습니다. 특히 RTLLM에서는 성능 하락 가능성이 남아 있습니다(Δ −4.27pp, 95% CI [−12.82, +4.27], 컴파일률 −8.55pp). 복잡한 FPGA·GPU·NPU 설계 능력의 향상이 검증된 버전은 아닙니다. 실사용에는 원본 모델을 권하며, 이 체크포인트는 연구·실험 용도로 사용하시기 바랍니다.

평가 조건은 thinking on, 최대 출력 65,536 토큰, 카드 권장 샘플링이다. 수치는 위 영문 표와 같다. 학습 데이터는 행 단위 허용 라이선스가 확인된 OpenRTLSet 코드를 시드로 쓴다. 그 설명을 보고 Qwen3.8 이 생성한 RTL 중 원본과 Yosys 제한 조건 동치를 통과한 1000 행이다. 사양 정답성이 증명된 것은 아니다. 일반 코딩 replay 317 행을 섞었다. 한계는 위 Limitations 와 같다. 1,000개 학습 사례에 대한 독립 시뮬레이션 감사에서 27개 출력 불일치와 244개 판정 불가 사례가 관측되었습니다. 일부 불일치는 시뮬레이션 환경의 차이일 수 있으며, 실제 기능 오류 비율은 확정되지 않았습니다. 이 사례들은 학습에 포함됐고 재학습은 하지 않았습니다.