Qwen3.6 27B MTPLX Optimized Quality FP16
This is the FP16 sibling artifact for Youssofal/Qwen3.6-27B-MTPLX-Optimized-Quality. It is intended for MTPLX's device-aware default routing on older Apple Silicon systems where FP16 may be preferable to BF16.
MTPLX policy:
- M1/M2 Apple Silicon: an Optimized Quality pick in
mtplx startand the MTPLX app auto-selects this FP16 artifact. - M3/M4/M5 and unknown hardware: the BF16 Optimized-Quality parent stays the default.
- Explicit
--modelalways overrides automatic routing.
The artifact preserves packed integer/quantized tensors (8-bit affine, group size 64) and converts BF16 floating tensors to FP16. See MTPLX_FP16_CONVERSION_MANIFEST.json for tensor-level conversion details and SHA256 checksums.
Validation (2026-07-07, M5 Max): last-position logits vs the BF16 parent agree at argmax on 16/16 checked positions (mean top-20 overlap 0.99); a greedy 30-token continuation matches the parent exactly. Under the MTPLX turbo profile the artifact measured 2.5x decode over its own true-AR baseline with snapshot-verified arms.
This model card is deliberately not a universal speed claim. Hardware-specific benchmarks should be reported separately.